1. The Field of the Invention
The present invention relates to via etch processing in which a via etch residue is removed after the etch. In particular, the present invention relates to a method of cleaning an etched via having polymer film residue thereon that forms in a dry anisotropic etch. The present invention accomplishes the cleaning method to remove the dry via etch residue with minimal damage to structures that have been exposed by the dry via etch.
2. The Relevant Technology
In the microelectronics industry, a substrate refers to one or more semiconductor layers or structures which include active or operable portions of semiconductor devices. The term substrate assembly is intended herein to mean a substrate having one or more layers or structures formed thereon. As such, the substrate assembly may be, by way of example and not by way of limitation, a doped silicon semiconductor substrate typical of a semiconductor wafer.
In semiconductor integrated circuits, construction of devices in stacked layers is required to facilitate the ever-present pressure upon the industry to miniaturize. Stacked device layers require interconnects to electrically wire the stacked devices together into a coherent integrated circuit. Formation of interconnect layers are made functional by interconnect signal lines that make contact between upper and lower conductive layers in the integrated circuit by way of vias though interlevel dielectric layers. For best operation of an integrated circuit that has multiple stacked layers with interconnects, lower conductive layers must not be damaged during formation of the via or the interconnect to be formed therein.
Various interlevel insulating layers are deposited on the integrated circuit during formation of the device. These layers separate the conductive layers from each other and act as insulators as well as structural supports. One method to form a via having an interconnect therein through these insulating layers is to etch through a mask to define a location for the interconnect via. Masks can be made of various materials, including curable polymers. After mask formation, a dry anisotropic etch is conducted to form the interconnect via. Anisotropic dry etching causes some of a polymer mask to partially dissolve and form a polymer film within the interconnect via during its formation. The polymer film can assist the dry anisotropic etch by resisting lateral etching by the etching medium.
During partial dissolution of the mask that occurs while the dry etch is progressing, lower level metallization layers can become exposed and may also be etched, either by design, or incidental to the etch. Etched metallization materials are often reactively incorporated into the polymer film as it forms upon the newly etched interconnect surfaces, including the exposed surfaces of lower level metallization layers. The polymer film formed during such etching needs to be removed to allow proper contact to be made in the interconnect via between conductive layers.
Because underlying metallization becomes incorporated into the polymer film, removal of the film with conventional photoresist solvents is often inadequate. Prior art methods of removal of the polymer films include dissolution through use of a solvent, acid, or plasma etch. During these processes, however, underlying metallization can also be removed in a way that compromises the integrity of the device that the underlying metallization is designed to contact.
FIGS. 1 through 4 depict formation of an interconnect via 12 as known in the prior art. In FIG. 1, an integrated circuit detail 10 is shown in cross-section, wherein a polymer mask 14 has been deposited and pattered upon an SiO.sub.2 isolation layer 18. A dry anisotropic etch has opened an interconnect via 12 that penetrates through each of isolation layer 18, a TiN anti-reflective layer 20, and partially into an aluminum alloy metallization layer 22.
Typical of the formation of interconnect via 12, there is illustrated in FIG. 1 further structures that connect an upper layer to a lower layer. A second conductive layer 24, that may comprise titanium nitride for example, is situated upon a first liner layer 26 that may comprise metallic titanium. Metallization layer 22 is in electrical contact with a tungsten plug 30 through second conductive layer 24 and first liner layer 26. A second liner layer 28 which can be by way of example a titanium nitride layer that lines plug 30 which is embedded in a lower insulation layer 32 that may be BPSG, by way of example. Plug 30 makes electrical contact with structures below lower insulation layer 32, such as an active area 38.
In FIG. 1 the results of a dry anisotropic etch are illustrated, wherein a polymer film 16 has been formed within interconnect via 12. Polymer film 16 was formed by partial dissolution of polymer mask 14 and chemical-reactive intermingling of etched metallization layer 22 with polymer mask 14.
FIG. 2 illustrates integrated circuit detail 10 following stripping of polymer mask 14. It can be seen that polymer film 16 formed within interconnect via 12 was not removed by stripping of polymer mask 14. According to methods of the prior art, a more aggressive stripping solution is required to remove polymer film 16 than a stripping solution used to remove polymer mask 14. While more aggressive stripping solution are desired, it is also desirable to avoid stripping solutions that are not environmentally inert.
FIG. 3 illustrates the results of a prior art effort to remove polymer film 16. Typically, a plasma etch or an etch known in the art as a piranha etch, which contains a solution of hydrogen peroxide and sulfuric acid, is used to remove polymer film 16. One skilled in the art will recognize that more aggressive etchants such as the piranha etch will remove a substantial portion of metallization layer 22, although the time required to remove polymer film 16 is held to a minimum. Thus, the acid or etchant used to remove polymer film 16 creates an undesirable pit 34 in metallization layer 22.
If a plasma etch is used to remove polymer film 16, undesirable pit 34 can also be undesirably formed in metallization layer 22 due to the overetching inherently required to insure complete removal of polymer film 16. If the etch is not performed long enough, some of polymer film 16 will not be removed. Thus, a plasma etch presents a tradeoff. Either holes are formed in metallization layer 22 or not all of polymer film 16 is removed.
Another problem encountered with plasma or acid etching is that such etching removes a portion of insulation layer 18 such that interconnect via 12 widens at least at an upper surface 40 of insulation layer 18. Widening of interconnect via 12 at upper surface 40 increases the size of interconnect via 12. Such widening, if not properly controlled, can cause interconnect via 12 to destructively overlap with other interconnect vias, causing a defect condition and thus reducing fabrication yield.
With over-aggressive etching, pit 34 may form within metallization layer 22. Pit 34 Makes filling of interconnect via 12 difficult because of an undercutting 42 into metallization layer 22 below an optional anti-reflective layer 20 and insulation layer 18. Pit 34 creates a thin structure 44 within metallization layer 22. Thin structure 44 can cause field failures of integrated circuit detail 10 by breach of metallization layer 22, for example, due to aluminum ion electromigration caused by heated structures and increased electrical resistance within thin structure 44. Electromigration eventually leads to additional thinning of thin structure 44 until metallization layer 22 becomes discontinuous and a field failure within integrated circuit detail 10 results.
FIG. 4 illustrates another prior art problem caused by aggressive etching to remove polymer film 16. When etching is too aggressive, pit 34 penetrates entirely through metallization layer 22 into other structures and metallization layer 22 is electrically disconnected. This type of problem arises during fabrication and is a yield-decreasing failure.
What is needed is a method of forming interconnect vias in integrated circuits that includes a polymer film removing process that effectively removes a polymer film without damaging an underlying metallization layer, and preferably by using environmentally inert processes.